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Anglický jazyk
Analysis and Design of Networks-on-Chip Under High Process Variation
Autor: Rabab Ezz-Eldin
This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion... Viac o knihe
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O knihe
This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns.
- Vydavateľstvo: Springer
- Rok vydania: 2015
- Formát: Hardback
- Rozmer: 241 x 160 mm
- Jazyk: Anglický jazyk
- ISBN: 9783319257648
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