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Anglický jazyk
CMOS Low Power Analysis
Autor: Vijay Sharma
In this thesis leakage reduction techniques like stack forcing, multiple threshold CMOS, variable threshold CMOS are explored, that mitigate leakage in circuits, operating in the active mode at various temperatures. Also, implications of technology scaling... Viac o knihe
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O knihe
In this thesis leakage reduction techniques like stack forcing, multiple threshold CMOS, variable threshold CMOS are explored, that mitigate leakage in circuits, operating in the active mode at various temperatures. Also, implications of technology scaling on the choice of techniques to mitigate total leakage are closely examined. The result is guidelines for designing low-leakage circuits in nanometer technology nodes. Logic gates in the 180nm, 130nm, 100nm and 70nm technology nodes are simulated and analyzed. Here delay analysis of various logic circuits are also examined.
- Vydavateľstvo: LAP LAMBERT Academic Publishing
- Rok vydania: 2011
- Formát: Paperback
- Rozmer: 220 x 150 mm
- Jazyk: Anglický jazyk
- ISBN: 9783844382778
Nemecký jazyk 